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HY5V56B(L/S)F-I Series
4 Banks x 4M x 16bits Synchronous DRAM
Preliminary DESCRIPTION
The HY5V56B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY5V56B(L)F is organized as 4banks of 4,194,304x16 HY5V56B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * * Single 3.30.3V power supply All device balls are compatible with LVTTL interface 54Ball FBGA (13.5mm x 8.0mm) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM or LDQM * * Internal four banks operation Programmable CAS Latency ; 2, 3 Clocks * * * Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst *
ORDERING INFORMATION
Part No.
HY5V56BF-HI HY5V56BF-8I HY5V56BF-PI HY5V56BF-SI HY5V56B(L)F-HI HY5V56B(L)F-8I HY5V56B(L)F-PI HY5V56B(L)F-SI
Clock Frequency
133MHz 125MHz 100MHz 100MHz 133MHz 125MHz 100MHz 100MHz
Power
Organization
Interface
Package
Normal
4Banks x 4Mbits x16 Low power
LVTTL
54ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Sep. 02
HY5V56B(L/S)F-I
BALL CONFIGURATION
9 8 7 3 2 1
A B C D E F G H J < Bottom View >
1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 A B C D E F G H J 7 VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD
54 Ball FBGA 0.8 mm Ball Pitch
< Top View >
Rev. 0.1/Sep. 02 3
HY5V56B(L/S)F-I
BALL DESCRIPTION
BALL OUT F2 F3 SYMBOL CLK CKE TYPE INPUT INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10
G9 G7,G8
CS BA0, BA1
INPUT INPUT
H7, H8, J8, J7, A0 ~ A12 J3, J2, H3, H2, H1, G3, H9, G2, G1 F8, F7, F9 F1, E8 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A9, E7, J9, A1, E3, J1 A7, B3, C7, D3, A3, B7, C3, D7 E2, G1 RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15
INPUT
INPUT INPUT I/O
Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask:Controls output buffers in read mode and masks input data in write mode Data Input/Output:Multiplexed data input/output ball
VDD/VSS VDDQ/ VSSQ NC
SUPPLY SUPPLY -
Power supply for internal circuits Power supply for output buffers No connection
HY5V56B(L/S)F-I
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer
Internal Row counter
CLK CKE CS RAS CAS WE UDQM LDQM State Machine State Machine State Machine State Machine Address buffers A12 A11 BA0 BA1 Mode Registers
Rev. 0.1/Sep. 02
4Mx16 Bank 3
Row active
Row Pre Decoders
4Mx16 Bank 2 X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders X decoders 4Mx16 Bank 1 4Mx16 Bank 0 DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
refresh
Column Active
Memory Cell Array
Column Pre Decoders Y decoders
DQ14 DQ15
Bank Select
Column Add Counter
A0 A1
Address Registers Burst Counter
CAS Latency
Data Out Control Pipe Line Control
5
HY5V56B(L/S)F-I
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any ball relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol -40 ~ 85 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=-40 to 85C)
Parameter Power Supply Voltage Input High voltage Input Low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0V 2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=-40 to 85C, VDD=3.30.3V, VSS=0V)
Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note
Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit
Rev. 0.1/Sep. 02
6
HY5V56B(L/S)F-I
CAPACITANCE (TA=25C, f=1MHz)
-H Parameter ball Symbol Min Input capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 CI1 CI2 CI/O 2.5 2.5 4.0 Max 3.5 3.8 6.5 Min 2.5 2.5 4.0 Max 4.0 5.0 6.5 pF pF pF -8/P/S Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output 50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=-40 to 85C, VDD=3.30.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Symbol Min. -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = +2mA
Note : 1.VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6
Rev. 0.1/Sep. 02
7
HY5V56B(L/S)F-I
DC CHARACTERISTICS II (TA=-45 to 85C, VDD=3.30.3V, VSS=0V)
Parameter Symbol Test Condition -HI Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other balls VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other balls VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active CL=3 CL=2
130 140 220 130 140 200 3 1.5 900 120
Unit -8I
120 2 mA 1
Note
-PI
110
-SI
110 mA 1
15 mA 15 5 mA 5
30 mA 20 110 120 200 110 mA 120 200 mA mA mA uA 2 3 4 5 1
IDD4 IDD5
tRRC tRRC(min), All banks active Normal
Self Refresh Current
IDD6
CKE 0.2V
Low Power SL Power
Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY5V56BF-HI/8I/PI/SI 4.HY5V56BLF-HI/8I/PI/SI 5.HY5V56BSF-HI/8I/PI/SI
Rev. 0.1/Sep. 02
8
HY5V56B(L/S)F-I
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-HI Parameter Symbol Min System Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW CAS Latency = 3 CAS Latency = 2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 7.5 1000 10 2.5 2.5 2.5 2 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.0 2.0 5.4 6 5.4 6 10 3 3 2.5 2 1 2 1 2 1 2 1 1 2.0 2.0 6 6 6 6 Max Min 8 1000 10 3 3 2.5 2 1 2 1 2 1 2 1 1 2.0 2.0 6 6 6 6 Max Min 10 1000 12 3 3 2.5 2 1 2 1 2 1 2 1 1 2.0 2.0 6 6 6 6 Max Min 10 1000 ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns -8I -PI -SI Unit Note
Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency = 3 CAS Latency = 2
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 0.1/Sep. 02
9
HY5V56B(L/S)F-I
AC CHARACTERISTICS II
-HI Parameter Symbol Min Operation RAS Cycle Time Auto Refresh RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output Hi-Z Power Down Exit Time Self Refresh Exit Time Refresh Time CAS Latency = 3 CAS Latency = 2 tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 65 20 45 20 15 1 0 2 5 2 0 2 3 2 1 1 100K 64 68 20 48 20 16 1 0 2 5 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 2 5 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 2 5 2 0 2 3 2 1 1 100K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 65 Max Min 68 Max Min 70 Max Min 70 Max ns -8I -PI -SI Unit Note
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.1/Sep. 02
10
HY5V56B(L/S)F-I
DEVICE OPERATING OPTION TABLE
HY5V56B(L)F-HI
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.0ns 2.0ns 2.0ns
HY5V56B(L)F-8I
CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs tRC 9CLKs 7CLKs 6CLKs tRP 3CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2.0ns 2.0ns 2.0ns
HY5V56B(L)F-PI
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2.0ns 2.0ns 2.0ns
HY5V56B(L)F-SI
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2.0ns 2.0ns 2.0ns
Rev. 0.1/Sep. 02
11
HY5V56B(L/S)F-I
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit H H H H H L H X L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X L L L H X L H X L L L X L L L X H L H X X H L X V X X X X X L L H L X X L X X X A9 ball High (Other balls OP code) MRS
Mode
CKEn-1 H H H
CKEn X X
CS L H L
RAS L X H L H
CAS L X H H L
WE L X
DQM X X
ADDR
A10/ AP OP code X RA L
BA
Note
H H H X X CA H L V V
X X
L L
X
L
H
L
L
X
CA H H
V X V
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.1/Sep. 02
12
HY5V56B(L/S)F-I
PACKAGE INFORMATION 54 Ball 0.8mm pitch 8.0mm x 13.5mm FBGA
0.80
13.50 6.40
0.450 0.80 6.40 8.00 0.340 1.070
Rev. 0.1/Sep. 02
13

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